Embodiments of the disclosure relate generally to a nonvolatile memory device and a method of manufacturing the same, and, more particularly, to the junction regions of a nonvolatile memory device.
In a nonvolatile memory device, memory cells for storing data are interconnected in series within the same string. The memory cells are electrically interconnected through junction regions within the same string.
FIG. 1 is a sectional view of a known nonvolatile memory device.
The nonvolatile memory device of FIG. 1 may be implanted by forming a number of gate lines on a semiconductor substrate 10 in which well and junction regions 10a and 10b are formed. For example, the gate lines may be classified into various types according to the function or structure. In FIG. 1, word lines WL0 to WL2 and a source select line SSL are shown as examples.
Each of the word lines WL and the source select line SSL may have a stack structure, including a gate insulation layer 12, a floating gate 14, a dielectric layer 16, a control gate 18, and a hard mask pattern 20. Here, the source select line SSL functions to transfer a driving voltage. Thus, a dielectric layer contact hole (ONC) is formed in the dielectric layer 16, thereby electrically connecting the floating gate 14 and the control gate 18. The word lines WL are coupled to the control gates of the memory cells, and the source select line SSL is coupled to the control gate of a source select transistor. For convenience of description, the junction regions formed between the word lines WL0 to WL2 are referred to as first junction regions 10a, and the junction region formed between the source select line SSL and the first word line WL0 is referred to as a second junction region 10b. 
The source select line SSL uses voltage higher than voltage used in the first to third word lines WL0 to WL2. Thus, the distance between the source select line SSL and an adjacent first word line WL0 is wider than a distance between the word lines WL0 to WL2. However, there is a limit to an increase of the distance between the source select line SSL and the adjacent first word line WL0 because of the degree of integration of nonvolatile memory devices. Accordingly, the electrical properties of the first word line WL0 of the word lines WL0 to WL2 is more likely to deteriorate than the other word lines.
For example, electrons may be trapped in the gate insulation layer (or a tunnel insulation layer) with the repetition of a program operation and an erase operation. The trapped electrons may cause an increase in the threshold voltage of the memory cell. Furthermore, a memory cell having a larger amount of electrons trapped in the gate insulation layer (or the tunnel insulation layer) has a higher program operation than other memory cell having a smaller amount of electrons trapped in the gate insulation layer (or the tunnel insulation layer). Accordingly, a distribution width of the threshold voltage of a corresponding nonvolatile memory device may increase. In particular, in the first word line WL0, the length of the second junction region 10b is long because the distance between the first word line WL0 and the source select line SSL is wide. Accordingly, the second junction region 10b has a higher capacitance than each of the first junction regions 10a between the word lines WL0 to WL2, which may change a distribution of the threshold voltages. Such the difference in the capacitance has an effect on the erase operation, which is described below with reference to FIG. 2, below.
FIG. 2 is a graph showing variations in the potential energy of the known nonvolatile memory device.
The graph of FIG. 2 shows the difference in the potential energy voltage for every well and junction region when the erase operation of the nonvolatile memory device is performed. The erase operation of a nonvolatile memory device in which P-wells are formed is described as an example. In an erase peripheralod, an erase voltage (e.g., 20 V) is applied to the P-well. Here, the potential energy of not only the P-well, but the second junction region 10b formed between the source select line SSL and the first word line WL0 increases, and the potential energy of the first junction regions 10a formed between the word lines WL0 to WL2 increases. In a discharge peripheralod subsequent to the erase peripheralod, the level of the erase voltage applied to the P-well is lowered. Here, a section A in which the potential energy changes is generated between the erase peripheralod and the discharge peripheralod. A width of the change is narrow because the erase voltage or a discharge voltage is directly applied to the P-well. A width of the change in the junction region between the word lines is slightly wider than that in the P-well.
Meanwhile, a width of the change in the second junction regions 10b between the source select line SSL and the first word line WL0 is wider than that in the junction region between the word lines because it is directly influenced by electrons trapped in the gate insulation layer 12 of the first word line WL0. If the reaction speed of the second junction region 10b is slow that that of other junction regions, many electrons can be generated because the leakage current is likely to occur. In particular, if the P-well is discharged prior to the second junction regions 10b and thus becomes 0 V, the erased floating gate 14 of the first word line WL0 becomes a positive potential state. Here, since the electrons generated in the second junction region 10b can enter the floating gate 14 of the first word line WL0, the cycling characteristic of the nonvolatile memory device may deteriorate.
Further, a nonvolatile memory device includes a number of junction regions. The junction regions are formed by performing an ion implantation process whereby impurity ions are implanted into a semiconductor substrate. The profile of the ion implantation process, such as the type of ions, the concentration of ions, or the implantation depth of ions, varies for every junction region. Accordingly, prior to the ion implantation process, a mask process of opening regions (i.e., targets), but defining regions (which are not targets) must be performed. Consequently, there is a problem in that a process of forming junction regions is complicated because the mask process must be repeatedly performed as many as the number of transistors including different junction regions.
Furthermore, to manufacture a nonvolatile memory device, a large number of unit processes must be performed. The unit processes include a stack process, an etch process, an ion implantation process, etc., and they are typically performed on a wafer basis. From among the unit processes, the ion implantation process is a process technique that is used to allow dopant ions, such as boron (B) and arsenic (As), to pass through the wafer surface by a strong electric field. If the junction regions are formed using this technique, the electrical properties of the transistor can be controlled.
Since transistors having different characteristics are formed on a wafer, the transistors must include different junction regions suitable for the characteristics. Accordingly, a process of forming and removing ion implantation masks for selectively opening the junction regions must be performed several times. However, the process of forming and removing the ion implantation masks causes to increase the process expenses and the turn-around time. Accordingly, efforts to reduce the process of forming the ion implantation masks are continuing.